1. Field of the Invention
The present invention relates to a semiconductor memory in which a save address is stored in an electrically writable fuse (E-Fuse).
2. Description of the Related Art
In general, a semiconductor memory comprises a redundancy circuit for replacing a spare cell a faulty cell which has been judged to be faulty by testing in order to improve the yield of products. This replacement is achieved by programming an address of a faulty cell, i.e., a save address in a fuse array after testing.
During normal operation, for example, if an external address which is identical to the save address stored in the fuse array is allocated to a chip, the spare cell is selected instead of the faulty cell. Thus, the faulty cell has been apparently saved, and the yield of products can be improved (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2002-197889).
As a fuse array for storing a save address, there is generally known a laser fuse for breaking a fuse by using a laser beam. Because a program of the save address for the laser fuse uses a laser beam, such programming can be carried out only in a wafer state, and cannot be carried out after an assembling process.
In recent years, there has been developed a semiconductor memory in which an address of a faulty cell which has been faulty in a test after the assembling process is programmed for a fuse array, and the fuse array is composed of an electrically writable fuse (hereinafter, referred to as an electrical fuse) in order to further improve the yield of products.
FIG. 1 shows essential portions of a conventional semiconductor memory comprising an electrical fuse.
A memory cell array 11 is allocated in a chip 10. The memory cell array 11 may be one of a plurality of memory blocks (for example, a bank). In this embodiment, the memory cell array 11 is assumed to include some of the periphery circuits such as a decoder, a sense amplifier, and a read/write circuit.
An external input/output terminal (DQ terminal) 12 is provided as an element for capturing write data in the chip 10 and for outputting read data to the outside of the chip. An input circuit 14A transfers to the memory cell array 11 the write data provided to the external input/output terminal 12. An output circuit 17A transfers to the external input/output terminal 12 the read data read out from the memory cell array 11.
An external input terminal (address terminal) 19A is provided as an element for capturing row/column address data in the chip 10 during normal operation and during testing. The row/column address data is provided to the memory cell array 11, and is used to select a memory cell.
In addition, during fuse programming after testing, for example, data A0 to A4 required for programming a save address in a fuse array are produced by a tester. The data A0 to A4 are supplied into the chip 10 via the external input terminal 19A.
The data A0 to A4 are provided to a decoder circuit DCi. The decoder circuit DCi decodes the data A0 to A4, and generates fuse program data D0 to D19. The fuse program data D0 to D19 determine a fuse targeted for fuse blowing.
A fuse program circuit FPi comprises a fuse array including a plurality of electrical fuses. The fuse program circuit FPi electrically breaks a capacitor insulating film of one electrical fuse (for example, capacitor) in a fuse array determined by the fuse program data D0 to D19. Finally, master data (1 bit) FMAST and save address data (a plurality of bits) FADDn are programmed for the fuse array.
The master data FMAST is provided as data for determining whether the fuse program circuit FPi is valid or invalid. In the case where the master data FMAST indicates that the fuse program circuit FPi is valid, the save address data FADDn programmed for the fuse program circuit FPi is valid.
A monitor circuit M is provided as a circuit for detecting whether or not the master data FMAST and save address data FADDn have been precisely programmed for the fuse array.
During normal operation, the fuse program circuit FPi outputs the master data FMAST and save address data FADDn. A redundancy circuit 21 compares the save address data FADDn with external address data in the case where the master data FMAST indicates that the fuse program circuit FPi is valid.
When both of the data coincide with each other, the redundancy circuit 21 outputs a replacement signal “Rep”. The memory cell array 11 selects a spare cell instead of a faulty cell upon the receipt of the replacement signal “Rep”.
The chip 10 includes a memory chip, an IC chip comprising a memory cell array, for example, a memory mixed IC chip, or a system LSI chip, etc. The type of the memory is not limited. This chip includes all memories such as DRAM, SRAM, FeRAM, MRAM, ROM, and flash memory.
Now, a description will be given with respect to examples of the decoder circuit DCi, fuse program circuit FPi, and monitor circuit M shown in FIG. 1.
In order to ensure clarity, presupposition is defined as follows. Four banks (memory cell array) are allocated in one chip 10. One decoder circuit DCi, one fuse program circuit FPi, and one redundancy circuit 21 are provided for one bank. One bank consists of, for example, a 16-row and 16-column matrix shaped memory cell array, and save address data FADD0 to FADD3 are composed of 4 bits.
FIG. 2 shows an example of the decoder circuit DCi (i=0, 1, 2, 3), and FIG. 3 shows examples of the fuse program circuit FPi (i=0, 1, 2, 3) and the monitor circuit M.
Four decoder circuits DC0, DC1, DC2, and DC3 exist corresponding to four banks 0, 1, 2, and 3, and four fuse program circuits FP0, FP1, FP2, and FP3 exist corresponding to four banks 0, 1, 2, and 3.
The data A0 to A4 generated by a tester (address data during fuse programming) are inputted to the decoder circuits DC0, DC1, DC2, and DC3.
The decoder circuit DC0 corresponding to bank 0 outputs fuse program data (decode signals) D0 to D4. The fuse program data D0 to D4 are inputted to a fuse program circuit FP0 which corresponds to bank 0.
The decoder circuit DC1 corresponding to bank 1 outputs fuse program data (decode signals) D5 to D9. The fuse program data D5 to D9 are inputted to a fuse program circuit FP1 which corresponds to bank 1.
The decoder circuit DC2 corresponding to bank 2 outputs fuse program data (decode signals) D10 to D14. The fuse program data D10 to D14 are inputted to a fuse program circuit FP2 which corresponds to bank 2.
The decoder circuit DC3 corresponding to bank 3 outputs fuse program data (decode signals) D15 to D19. The fuse program data D15 to D19 are inputted to a fuse program circuit FP3 which corresponds to bank 3.
As shown in Table 1, one of the fuse program data (decode signals) D0 to D19 is set to “H” in response to values of the data A0 to A4 generated by a tester.
TABLE 1Position of EF to be broken (programmed)Bank 0Bank 1Bank 2Bank 3Decode signalMASTA0A1A2A3MASTA0A1A2A3MASTA0A1A2A3MASTA0A1A2A3set to “H”D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19DataA001010101010101010101(address)A100110011001100110011generatedA200001111000011110000by testerA300000000111111110000A400000000000000001111
Now, a specific example will be described here.
For example, assume that, as a result of testing, a faulty cell exists in bank 0, and the faulty addresses (save addresses) A0, A1, A2, and A3 are “0”, “0”, “0”, and “1”. The save address may be a row address (row save) or may be a column address (column save).
First, during fuse programming after testing, the address data A0, A1, A2, A3, and A4 generated by a tester are limited to “0”, “0”, “0”, “0”, and “0”. In this case, as shown in Table 1, only data D0 of the fuse program data D0 to D19 is set to “H”.
As a result, MAST in the fuse program circuit FP0 of FIG. 3 is set to “H”, and an N-channel MOS transistor Tr2 in which MAST is to be inputted to a gate is set to an ON state. An N-channel MOS transistor Tr1 is provided as a barrier transistor for mitigating a high voltage, and is always in an ON state.
Therefore, a high voltage is applied to an electrical fuse (for example, capacitor) EF associated with FMAST; a capacitor insulating film of the electrical fuse EF is broken, and the fuse program circuit FP0 is valid.
Next, the address data A0, A1, A2, A3, and A4 generated by a tester are set to “0”, “0”, “1”, “0”, and “0”. In this case, as shown in Table 1, only data D4 of the fuse program data D0 to D19 is set to “H”.
As a result, A3 in the fuse program circuit FP0 of FIG. 3 is set to “H”, and the N-channel MOS transistor Tr2 in which A3 is to be inputted to a gate is set to an ON state. The N-channel MOS transistor Tr1 is provided as a barrier transistor for mitigating a high voltage, and is always in an ON state.
Therefore, a high voltage is applied to an electrical fuse (for example, capacitor) EF associated with FADD3, and a capacitor insulating film of the electrical fuse EF is broken.
Due to the above fuse programming operation being operated twice, “0”, “0”, “0”, and “1” are programmed as save addresses A0, A1, A2, and A3 in the fuse program circuit FP0.
In FIG. 3, “1” is set in the case where the capacitor insulating film of the electrical fuse EF has been broken (in a conductive state), and “0” is set in the case where the film is not broken (in a non-conductive state). A circuit for reading out master data (1 bit) FMAST and save address data (4 bits) FADD0 to FADD3 is not shown.
In examples of FIGS. 2 and 3, a save address is generated by a tester (device type compatible with save address generation). In this case, the tester comprises a function for testing all the memory cells which configure a memory cell array and a function for representing an address of a memory cell which has been determined to be faulty on a map (Fail Address Map: FAM), and obtaining a save address (save solution) for saving a faulty cell most effectively.
When a save address is programmed for the fuse program circuit FPi, in this example, the decoder circuit DCi of FIG. 2 is provided in a chip in order to reduce the number of external terminals used for the programming. That is, when the decoder circuit DCi is used, the number of external terminals may be 5 (A0 to A4). When the decoder circuit DCi is not used, the number of external terminals must be equal to at least the number of fuses (20).
FIG. 4 shows an example of specific operating waveform during fuse programming.
This operating waveform is provided as an example of programming “0”, “0”, “0”, and “1” as the save addresses A0, A1, A2, and A3 with respect to bank 1.
First, a fuse program signal (fuse program entry number) PROGRAM is set to “H”, and a fuse program mode is established. At this time, an N-channel MOS transistor N4 in the fuse program circuit FPi of FIG. 3 is set to an ON state. In addition, a VBP level (electrical potential) is set at a value which is sufficiently large for fuse breakage.
The VBP level is set at a value which is sufficiently large only when the fuse program mode is established in order to ensure low power consumption during chip operation. When VBP is not used, for example, a grounding electrical potential is set.
Next, FMAST programming is carried out.
In synchronism with a fall edge of a row address strobe signal/RAS (a turning point from “H” to “L”), the address signals A0 to A4 generated by a tester are captured in the decoder circuit DCi of FIG. 2. The address signals A0 to A4 are obtained as “1”, “0”, “1”, “0”, and “0”. As shown in Table 1, a decode signal D5 corresponding to FMAST in bank 1 is set to “H”.
Because of this, VBP is provided at one end of only an electrical fuse EF which corresponds to FMAST in bank 1, and a grounding electrical potential is provided at the other end of the fuse. As a result, a remarkable difference in electrical potential occurs at both ends of the capacitor insulating film of the electrical fuse (for example, capacitor) EF which corresponds to FMAST in bank 1, the capacitor insulating film is broken, and “1” (=valid)” is programmed.
Next, FADD3 programming is carried out.
Here, “0” is programmed with respect to FADD0 to FADD2. However, an initial state (an unbroken state) of the electrical fuse EF is set to “0”. Therefore, there is no need to carry out fuse programming with respect to FADD0 to FADD2.
In synchronism with the fall edge of the row address strobe signal/RAS (the turning point from “H” to “L”), the address signals A0 to A4 generated by a tester are captured in the decoder circuit DCi of FIG. 2. The address signals A0 to A4 are obtained as “1”, “0”, “0”, “1”, and “0”. As shown in Table 1, a decode signal D9 corresponding to ADD3 in bank 1 is set to “H”.
Because of this, VSP is provided at one end of only an electrical fuse EF which corresponds to FADD3 in bank 1, and a grounding electrical potential is provided to the other end of the fuse. As a result, a remarkable difference in electrical potential occurs at both ends of the capacitor insulating film of the electrical fuse (for example, capacitor) EF which corresponds to FADD3 in bank 1, the capacitor insulating film is broken, and “1” is programmed.
In this example, one ends of all the electrical fuses EF are connected in common, and VBP (high electrical potential) is provided at one ends of the fuses. Therefore, fuse programming is carried out on one bit by one bit basis. In this example, at least one programming operation (FMAST=1 bit) and a maximum of 5 programming operations (FMAST+ADD0 to ADD3=5 bits) are carried out for one save address.
In general, after a save address has been programmed, verification for verifying whether or not the save address has been precisely programmed is executed.
A fuse programming operation is executed only for a fuse targeted for “1”-programming, because the initial state of the electrical fuse is set to “0”, as described above.
In contrast, a verifying operation is provided to verify whether or not the save address has been precisely programmed. Thus, for example, all the electrical fuses (FMAST, FADD0 to FADD3) are programmed sequentially on one bit by one bit basis.
In this case, the verifying operation starts from FMAST of bank 0, for example, advances in ascending order of FADD0, FADDS1, FADD2, and FADD3 of bank 0, and further, advances in ascending order of bank 1, bank 2, and bank 3.
In verification relevant to an electrical fuse for which “1”-programming has been executed, when EFmoni is set to “H”, programming OK is produced. When it is set to “L”, programming NG is produced. In verification relevant to an electrical fuse for which “1”-programming has not been executed, when EFmoni is set to “L”, programming OK is produced. When it is set to “H”, programming NG is produced.
In the case where one monitor circuit is provided for one bank, verification operations in a plurality of banks can be executed in parallel. In addition, in the case where only one monitor circuit is provided for a plurality of banks, the verifying operations are carried out sequentially on a one bank by one bank basis.
Verifying operation is eventually carried out as verification of “1”-programming relevant to an electrical fuse. Therefore, the verifying operation may be targeted for only an electrical fuse for which “1”-programming has been carried out instead of carrying out the above operation for all the electrical fuses.
In this case, when “1”-programming is OK, a current path from VBP to Vss is produced via the electrical fuse EF and transistors Tr1, Tr2, and Tr3. On the other hand, when “1”-programming is NG, no fuse is broken, and thus, such a current path is not produced.
According to a verifying operation targeted for only an electrical fuse for which “1”-programming has been carried out, an address used during fuse programming may be allocated from a tester to a chip again. Therefore, the verifying operation can be carried out simply and within a short time.
FIG. 5 shows an example of operating waveform when a save address is verified.
This operating waveform relates to a verifying operation targeted for only the electrical fuse for which “1”-programming has been carried out.
First, a test mode verify signal TMVERIFY is set to “H”, and a verify mode is established. At this time, a transfer gate TG in the monitor circuit M of FIG. 3 is set to an ON state. In addition, a VBP level (electrical potential) is set to “H”, for example, a power supply potential Vdd.
The VBP level is set to “H” only when the verify mode is established in order to ensure low power consumption during chip operation. When VBP is not used, for example, a grounding electrical potential is set.
First, verification of FADD0 in bank 0 will be described here.
In synchronism with the fall edge of the row address strobe signal/RAS, the address signals A0 to A4 generated by a tester are captured in the decoder circuit DCi of FIG. 2. The address signals A0 to A4 are obtained as “1”, “0”, “0”, “0”, and “0”. As shown in Table 1, a decode signal D1 corresponding to FADD0 in bank 0 is set to “H”.
Because of this, VBP is provided at one end of only an electrical fuse EF which corresponds to FADD0 in bank 0, and a grounding electrical potential is provided at the other end of the fuse. As a result, the value of EFmoni changes according to a state of the electrical fuse EF which corresponds to FADD0 in bank 0.
For example, “0”-programming has been executed for an electrical fuse associated with FADD0 in bank 0.
In this case, as shown in the figure, when no current iPD flows and EFmoni is set to “L”, the fuse associated with FADD0 in bank 0 is not broken. Thus, it is possible to check that “0” has been precisely programmed. On the other hand, when a current iPD flows and EFmoni is set to “H”, the fuse associated with FADD0 in bank 0 is broken. Thus, “1” is assumed to have been mistakenly programmed.
Now, verification of FMAST in bank 1 will be described here.
In synchronism with the fall edge of the row address strobe signal/RAS, the address signals A0 to A4 generated by a tester are captured in the decoder circuit DCi of FIG. 2. The address signals A0 to A4 are obtained as “1”, “0”, “1”, “0”, and “0”. As shown in Table 1, a decode signal D5 corresponding to FMAST in bank 1 is set to “H”.
Because of this, VBP is provided at one end of only an electrical fuse EF which corresponds to FMAST in bank 1, and a grounding electrical potential is provided at the other end of the fuse. As a result, the value of EFmoni changes according to a state of the electrical fuse EF which corresponds to FMAST in bank 1.
For example, “1”-programming has been executed for the electrical fuse associated with FMAST in bank 1.
In this case, as shown in the figure, in the case where a current iPD flows and EFmoni is set to “H”, the fuse associated with FMST in bank 1 is broken. Thus, it is possible to check that “1” has been precisely programmed. On the other hand, in the case where no current iPD flows and EPmoni is set to “L”, the fuse associated with FMAST in bank 1 is not broken. Thus, “0” is assumed to have been mistakenly programmed.
FIG. 6 shows a test flow when a laser fuse is used.
In this case, in a test process at a wafer stage, for example, in a die sort test D/S, testing is executed by a tester capable of producing a save address. During save address programming, fuse breakage is executed by a laser machine. Then, it is tested whether or not a faulty cell has been precisely replaced with a spare cell.
In the case where the laser fuse is used, saving of a faulty cell can be carried out only at the wafer stage, and cannot be carried out after an assembling process. Testing at the wafer stage is carried out only under the condition of a predetermined temperature (for example, only at a high temperature) in view of a relation with a test time. In addition, a signal cable for transmitting a tester signal to a chip is too long to carry out testing for high speed operation. Therefore, when a faulty cell has been produced during a test process after the assembling process, for example, during a low temperature test LT, a high temperature test HT or the like, even if a faulty cell is produced, such a faulty cell cannot be saved.
FIG. 7 shows a test flow when an electrical fuse is used.
In this case, in a test process at a wafer stage, for example, in a die sort test D/S, testing is executed by a tester capable of producing a save address in the same manner as when a laser fuse is used. However, save address programming can be electrically carried out without a laser machine.
Therefore, a process for moving a wafer to a laser machine is eliminated, and thus, wafer touching up to the assembling process can be reduced. This means improved efficiency in manufacturing a semiconductor memory.
Then, a test process is carried out for whether or not a faulty cell has been precisely replaced with a spare cell.
In the case where the electrical fuse is used, saving of a faulty cell can be carried out after the assembling process. For example, in a test process after the assembling process, for example, during a low temperature test LT, a high temperature test HT or the like, testing is executed by means of a test capable of producing a save address. Then, save address programming is electrically executed, and the yield of products can be improved.
However, in a test flow using a conventional electrical fuse, save addresses (save solutions) must be obtained on a test by test basis. In addition, this save address must be obtained by a tester incorporating a FAM (Fall Address Map) function, for example. The tester incorporating the FAM function is very expensive. If this tester is used, a testing cost cannot be reduced.
In testing chips after the assembling process, a plurality of chips are tested at the same time. During one test, there is almost no case in which save addresses coincide with each other in all the chips targeted for testing. That is, for the chips after the assembling process, fuse programming operation is individually carried out on a chip by chip basis.
A tester cannot execute an operation for carrying out a test and producing a save solution during a period in which fuse programming operation is in progress. As a result, a FAM function cannot be used during the period.
Namely, in the conventional technique, an expensive tester incorporating a FAM function must be used. Further, there is a problem that this expensive tester cannot be used efficiently.
In the meantime, a bit failure such as short-circuit between bit lines primarily causes a faulty memory cell after the assembling process. The failure rate of bit failure is prone to increase as items are produced at a higher speed operation.
It is realistically impossible to detect such a bit failure during a die sort test at a wafer stage for one of the reasons stated below.
<1> Test strength or sensitivity must be increased;
<2> A large amount of die sort time is required; and
<3> The lowered yield due to overkill is considered.
A bit failure must be saved in a test process after the assembling test.
If at least a failure of a memory cell which occurs after such an assembling process can be saved without using an expensive tester incorporating FAM, it is very effective for improvement of test efficiency and lowering a test cost.